Responsibilities

• Collaborate with development teams for provisioning front-end and back-end & databases across multiple environments.
• Configure, troubleshoot, upgrade, and optimize systems built with EKS, EFS, Lambda, Route53, ECR, EC2, RDS, VPC, S3, ELB, and more.
• Proactively monitor performance and stability of our cloud platform serving a global consumer base.
• Automate Kubernetes deployment workflows and operations tasks using Jenkins.
• Participate in an on-call rotation shared with our US colleagues in a follow-the-sun model.
• Collaborate broadly within drop thought to develop cloud-native solutions on diverse business problems.

 Requirements

• Minimum 5years of relevant professional experience.
• 3 years working with AWS to develop or operate large-scale customer-facing applications
• Excellent written and verbal communication and a collaborative approach. This is a team-player role.
• Minimum 2years working with creating, building and maintaining Docker files and images.
• Solid Linux system administration, troubleshooting and performance analysis skills – (Ubuntu/Red Hat platforms)

 Nice to Have Skills

• Experience in managing highly-available, customer-facing environments on AWS or other PaaS offerings.
• Troubleshooting and performance tuning of containerized microservice deployments.
• Experience in building microservice based applications on container orchestration platforms such as Kubernetes, OpenShift, etc.
• Experience with web service operations – incident triage, response, troubleshooting, analysis, and reporting.
• We love generalists. You should have hands-on skills with at-least 50% (75% for Senior level) of the following:
  • Linux, NFS, Bash
  • Jenkins, Git
  • Redis, MySQL, PostgreSQL
  • Nginx, Apache, Haproxy
  • ElasticSearch, Kibana, FluentD, Jaeger
  • CDNs, DNS
  • RESTFUL APIs
  • SSL – LetsEncrypt and other vendors.
  • Docker, containerd
  • Network Analysis Tools and other CLI Tools
  • AWS APIs, AWS Lambda, RDS, EKS, ECS
  • Professional software development experience in an Agile Development environment is a definite plus

Share your resumes to  support@chipwaretechnologies.com

The post Opening for Senior DevOps Engineer appeared first on Chipware Technologies Private Limited.

A Unified DDM System is a Major Competitive Advantage :
The majority of data management problems associated with integrating large designs and the associated software can be eliminated if all the data is managed in a single unified DDM system, which could exist at a single design center, or could be distributed around the world. ENOVIA Synchronicity DesignSync Data Manager is the DDM system of choice to make such a vision a reality. In 13 of the top 15 global semiconductor companies and in hundreds of other organizations, ENOVIA Synchronicity DesignSync Data Manager is the standard for management of complex EDA data created by hardware design tools from companies such as Cadence, Synopsys and Mentor Graphics. But, ENOVIA Synchronicity DesignSync Data Manager is also uniquely suited for the management of RTL Verilog or VHDL design, cell library development, or even documentation development. Plug-ins for the Microsoft Visual Studio and Eclipse IDEs (Integrated Development Environment) are included with ENOVIA Synchronicity DesignSync Data Manager for use by software designers.

ENOVIA Synchronicity DesignSync Data Manager enables individual design teams to independently release intellectual property (IP) modules, while the integration of multiple modules can be managed at a higher level of abstraction. A single command can fetch an entire design hierarchy, and another single command can create an immutable release of the same hierarchy. Inefficient and error prone manual integration procedures can be completely eliminated. Imagine what that would mean in practice at your company!

The post ENOVIA Synchronicity DDM appeared first on Chipware Technologies Private Limited.

Submit, Integrate, Test, and Release – SITaR ENOVIA Synchronicity DesignSync Data Manager provides an intuitive built-in workflow called SITaR (Submit, Integrate, Test, and Release). SITaR consists of a set of commands that leverage the power of module-based design in an environment consisting of multiple design modules aggregated together by an integrator into a higher level system. Though individual design blocks (modules) may be contributed by different teams, design at the block level cannot occur in a vacuum. Simulations must include interactions with the other blocks in the design.

SITaR is based on the notion that there are two fundamental “roles” in play in such a design:
a “designer” is someone who is contributing at the block level. An “integrator” is responsible for integrating blocks together into a toplevel design, testing the system, and releasing the stable “baseline” (a system level configuration of blocks) from which all subsequent block level development occurs.

Working within such a flow, a designer would fetch the current stable baseline into a workspace. The block the designer is working on would then be put in an “edit” mode, and design activities proceed. All simulation takes place in the context of the baseline consisting of all the other blocks. The key here is that design work and simulation is NOT done with work-in-process configurations of other blocks, but only in the context of the stable baseline.

When work is complete, the designer “submits” his module for possible integration into a newer baseline. The integrator monitors the submission queue, which could contain submissions for multiple blocks, and is able to build a workspace containing any mixture of submitted blocks. This is the “Integrate” step in SITaR. Regression tests are performed against the newly integrated set of blocks (the “Test” step in SITaR), and if deemed stable by the integrator, can be released as a new stable baseline (the “Release” step in SITaR). Designer workspaces could then be updated, fetching the baseline for all blocks for which editing activity is not occurring.

Thus, ALL design work at the block level is performed in the context of a stable baseline of the rest of the blocks in the design. All this activity is performed using simple and intuitive commands such as “sitr submit,” or “sitr integrate,” alleviating the need to educate the contributing teams in the use of the more fundamental module design command set, or with complicated handoff and tagging schemes.

SITaR commands wrap the underlying module commands such that the power of the module-based DDM architecture is leveraged in the context of this well-defined use model.

The post SITaR ENOVIA DesignSync Data Manager appeared first on Chipware Technologies Private Limited.

Every member you add to a team exponentially increases the number of relationships and the complexity of communication. This is why simply adding people rarely works without also identifying fundamental changes in tools and processes. Teams may need more people, but first and foremost, they need ways to improve team performance and communication, regardless of size and location.
This is the problem that we solve with ENOVIA Pinpoint.

The post ENOVIA Pinpoint Now. appeared first on Chipware Technologies Private Limited.

Enable collaborative design for complex semiconductor projects:

Dassault Systèmes Silicon Thinking Semiconductor Collaborative Design process integrates deep design analytics from ENOVIA® Pinpoint® and design data management from ENOVIA Synchronicity® DesignSync® to enhance team productivity for IC design. This process experience is used today by over 120 IC development organizations around the world to boost design team productivity.

ENOVIA Synchronicity DesignSync :
ENOVIA Synchronicity DesignSync helps centralize IC design data management for large, distributed projects. Design data is captured directly from electronic design automation (EDA) tools into a hierarchical data structure, which then provides coordinated access for distributed design teams. This hierarchical structure directly supports an IP-block assembly approach for rapidly designing customer-specific ICs. It helps simplify and speed integration of design sub-elements into the overall IC design, facilitating design reuse.

ENOVIA Pinpoint :
ENOVIA Pinpoint provides managers with dashboards and graphical analytics to assess and accelerate design closure. ENOVIA Pinpoint enables analysis of diverse design, simulation, and testing data with historical timelines to help you see where projects might be diverging from planned milestones. Project managers and designers have a shared view from which to make joint project management decisions.
To help ensure that complex integrated designs succeed, the right foundation for collaborative design and information systems is essential. Dassault Systèmes Silicon Thinking Semiconductor Collaborative Design process:
• Scales across large, distributed teams
• Supports IP reuse and variant optimization
• Works with multiple application platforms and keeps designers “designing”
• Maximizes information access
• Accelerates project decision making through automated, advanced analytics, and dashboards.

The post SEMICONDUCTOR COLLABORATIVE DESIGN PROCESS appeared first on Chipware Technologies Private Limited.

Dassault Systeme ENOVIA Synchronicity® DesignSync® Data Manager is used by semiconductor companies to manage the hardware and software data in their products. Data can be managed at both the detailed file/directory level, and at a “modular” level of abstraction. As such, design data contributed by individual teams can be seamlessly integrated into higher level designs.

Key Benefits

• Connect and manage your entire design chain with a unified DDM system.

• Significantly boost design productivity for a rapid payback and strong ROI.

• Maximize your ability to reuse existing designs and embedded software.

• Manage your design hierarchy as part of the design process.

• Utilize an intuitive built-in Submit, Integrate, Test, and Release (SITaR) workflow.

• Reduce time-to-market by increasing collaboration efficiency.

• Win first-to-market advantage.

• Manage complex data types from a variety of EDA tool vendors.

• Manage software projects using the Microsoft Visual Studio and Eclipse plug-ins.

The post DesignSync Data Manager appeared first on Chipware Technologies Private Limited.

ENOVIA Pinpoint provides your team with the information they need to get your design closed and taped-out  sooner. Rather than providing another tool that generates yet more data, we’ve focused ENOVIA Pinpoint on specific areas that help teams work better together. It provides actionable information to engineers and managers by extracting the critical metrics from existing tools at each step in the flow, and applying proprietary visualization techniques for relevance and context. All of the information resides on a central project server accessed through links and a browser, enabling communication and collaboration by team members. ENOVIA Pinpoint enables your entire team to work more efficiently to achieve your goals in complex designs.

Every manager knows that it’s the problems they see early that can be easily solved. These are not the ones that disrupt projects and careers. It’s the ones nobody saw coming until it was too late to do anything about without painful and time-consuming solutions. From the outset of physical design work, ENOVIA Pinpoint enables managers to see and analyze the entire progress of the design — to see how metrics are trending toward their goals. ENOVIA Pinpoint takes the mind boggling arrays of multi-dimensional data, analyzes and rolls them up in a simple visual dashboard with historical timelines to help you see where things might be trending off track. This provides context and improves communication between engineers and managers.

When the information is available, managers can use it to make better decisions. But you need high quality, reviewed information to make sure decisions are valid . This comes from the engineers actively using the tool to solve their problems. We’ve worked hard to make ENOVIA Pinpoint a tool for engineers as well as managers. ENOVIA Pinpoint provides sufficient detail for engineers to quickly find solutions to the problems in the design. We believe this is critical to any collaboration tool – providing fast, easy-to-access information that expedites and improves the decisions each engineer is making. ENOVIA Pinpoint provides visualization that helps engineers see the problem in a form they can act on, as well as communicate more accurately with their counterparts whether they are across the hallway or across the globe.

How expensive is a tapeout delay of one day? One week? How often do engineers work extra days to solve a problem that someone’s expertise could certainly help them solve, except for the fact that communicating about it and arranging effective collaboration is too difficult? Designers tell us this is one of the most frustrating challenges in today’s designs.

Dassault Systèmes has a well-established history in physical design tools and technology, and ENOVIA Pinpoint understands physical design data natively. It applies this technology to provide engineers with ways to see and communicate the issues they are working to solve. ENOVIA Pinpoint also enables engineers to see a broader context when looking at multiple experiments. They can see that even though timing was better for one experiment, the utilization won’t allow them to close that version, or the power became excessive.

Ultimately, ENOVIA Pinpoint helps individuals and teams make decisions that cannot be made in the absence of the information it provides. It brings focus to a myriad of factors that must be considered in design closure, and keeps teams current with design flow progress and on the same page. At the same time it helps managers to see and understand the status of all of the blocks in the design, based on objective information. This helps you get your designs done in a shorter time and with less risk.

The post Get Your Design Done! appeared first on Chipware Technologies Private Limited.

Everyday, chip tapeouts are slipping schedule. The managers wonder why they didn’t see the issues sooner. The engineers grapple with communicating and resolving the issues. These are skilled teams of engineers working overtime to get things done. Closure always seems a few days away, but continues to elude them.

This is the reality of physical design today and it will only get more difficult as chip complexity and data size continues to grow. In the past, teams sought new tools to deal with the additional technology challenges of a new process node. But even with the latest tools to place the design faster, make better clock-trees, etc., the fundamental problem of organizing the globally distributed team to push through the unknowns remains as the biggest risk to chip success.

Every run through the physical design flow can generate hundreds of GBs of data. Data is not the problem; lack of information is. Extracting meaning from the vast pools of enterprise data is exceedingly complex, and impossible without tool support. What were the metrics of the design two weeks ago? How much change did that last ECO actually introduce into the netlist ? These questions point the way to critical improvements today, but finding the information that you need to answer them must be made more practical.

Every member you add to a team exponentially increases the number of relationships and the complexity of communication. This is why simply adding people rarely works without also identifying fundamental changes in tools and processes. Teams may need more people, but first and foremost, they need ways to improve team performance and communication, regardless of size and location.
This is the problem that we solve with Dassault Systemes ENOVIA Pinpoint.

The post Why ENOVIA Pinpoint Now ? appeared first on Chipware Technologies Private Limited.

Turn Technical Complexity into Market Profitability

Advancements in integrated circuit (IC) density and competition for market leadership drive
demand for more complex devices from semiconductor manufacturers. To compete successfully,
manufacturers must use teams of diverse design specialists and complex project workflows to
maximize device differentiation and team productivity. As a result, IC projects carry increasing
business risk.
Dassault Systèmes Silicon Thinking Industry Solution Experience provides a portfolio of IC design
and engineering performance enhancements that help mitigate project risk, shorten time-to-market,
and increase product quality and yield. Silicon Thinking provides these benefits through:
• Efficient intellectual property (IP) management and reuse
• Graphical analytics to manage design closure
• Instant access to the latest design data for all design teams
• End-to-end traceability, from requirements to verification and validation
• Packaging reliability simulation and testing
• Enhanced product variation and defect management
With this solution portfolio, semiconductor manufacturers can more quickly and easily untangle
the simultaneous challenges they face from the demands of increasing chip complexity, lowering power consumption, and achieving faster time-to-production and higher yields.

SEMICONDUCTOR COLLABORATIVE DESIGN PROCESS
Enable collaborative design for complex semiconductor projects :
Dassault Systèmes Silicon Thinking Semiconductor Collaborative Design process integrates deep design analytics from ENOVIA® Pinpoint® and design data management from ENOVIA Synchronicity® DesignSync® to enhance team productivity for IC design. This process experience is used today by over 120 IC development organizations around the world to boost design team productivity.
ENOVIA Synchronicity DesignSync
ENOVIA Synchronicity DesignSync helps centralize IC design data management for large, distributed projects. Design data is captured directly from electronic design automation (EDA) tools into a hierarchical data structure, which then provides coordinated access for distributed design teams. This hierarchical structure directly supports an IP-block assembly approach for rapidly designing customer-specific ICs. It helps simplify and speed integration of design sub-elements into the overall IC design, facilitating design reuse.
ENOVIA Pinpoint
ENOVIA Pinpoint provides managers with dashboards and graphical analytics to assess and accelerate design closure. ENOVIA Pinpoint enables analysis of diverse design, simulation, and testing data with historical timelines to help you see where projects might be diverging from planned milestones. Project managers and designers have a shared view from which to make joint project management decisions.
To help ensure that complex integrated designs succeed, the right foundation for collaborative design and information systems is essential. Dassault Systèmes Silicon Thinking Semiconductor Collaborative Design process:
• Scales across large, distributed teams
• Supports IP reuse and variant optimization
• Works with multiple application platforms and keeps designers “designing”
• Maximizes information access
• Accelerates project decision making through automated, advanced analytics, and dashboards.

The post Silicon Thinking Experience appeared first on Chipware Technologies Private Limited.

ENOVIA® Synchronicity® DesignSync® Data Manager is used by semiconductor companies to manage the hardware and software data in their products. Data can be managed at both the detailed file/directory level, and at a “modular” level of abstraction. As such, design data contributed by individual teams can be seamlessly integrated into higher level designs

Key Benefits

• Connect and manage your entire design chain with a unified DDM system.

• Significantly boost design productivity for a rapid payback and strong ROI.

• Maximize your ability to reuse existing designs and embedded software.

• Manage your design hierarchy as part of the design process.

• Utilize an intuitive built-in Submit, Integrate, Test, and Release (SITaR) workflow.

• Reduce time-to-market by increasing collaboration efficiency.

• Win first-to-market advantage.

• Manage complex data types from a variety of EDA tool vendors.

• Manage software projects using the Microsoft Visual Studio and Eclipse plug-ins.

The post DesignSync Data Manager appeared first on Chipware Technologies Private Limited.